Title :
Design and analysis of the S-band PLL frequency synthesizer with low phase noise
Author :
Ma, Haihong ; Tang, Xiaohong ; Xiao, Fei ; Tan, Chizhou
Author_Institution :
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Sichuan, China
Abstract :
Controlled by a single chip, the S-band PLL frequency synthesizer at 2.82GHz with low phase noise is designed. Based on the study of PLL, the requirements for the phase noise of the crystal reference oscillator are theoretically estimated. And an effective method to completely eliminate the spurs caused by the single chip is presented. The phase noise of 2.82GHz PLL frequency synthesizer at 10 kHz offset is -94.3dBc/Hz, the reference spurs is better than -90dBc and the output power is over 18dBm.
Keywords :
crystal oscillators; frequency synthesizers; phase locked loops; phase noise; 10 kHz; 2.82 GHz; S-band PLL frequency synthesizer; crystal reference oscillator; phase locked loop; phase noise; Estimation theory; Frequency conversion; Frequency synthesizers; Low pass filters; Performance analysis; Phase detection; Phase estimation; Phase locked loops; Phase noise; Voltage-controlled oscillators;
Conference_Titel :
Microwave Conference Proceedings, 2005. APMC 2005. Asia-Pacific Conference Proceedings
Print_ISBN :
0-7803-9433-X
DOI :
10.1109/APMC.2005.1606591
