Design of an embedded fully-depleted SOI SRAM

Author

Sung, Raymond J. ; Koob, John C. ; Brandon, Tyler L. ; Elliott, Duncan G. ; Cockburn, Bruce E.

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2001

fDate

2001

Firstpage

13

Lastpage

18

Abstract

We describe the design of an embedded 128-Kb Silicon-On-Insulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25-μm fully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presented. The impact of the floating body effect is investigated for both memory reads and writes. We describe threshold mismatch effects in the sense amplifier that result from the floating body voltage. Floating body effects are compared against simulated results for an SRAM designed in a 0.25-μm partially-depleted SOI process

Keywords

CMOS memory circuits; SRAM chips; integrated circuit layout; random-access storage; silicon-on-insulator; 0.25 micron; 128 Kbit; SOI memory core layout; embedded SOI CMOS SRAM; floating body effect; floating body voltage; fully-depleted SOI SRAM; integrated circuit; massively-parallel data processing; pitch-matched processing elements; sense amplifier; threshold mismatch effects; CMOS process; CMOS technology; Capacitance; Circuit simulation; FETs; Insulation; Random access memory; Semiconductor films; Silicon on insulator technology; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945223

Filename

945223