Initial global routing in floorplanning by EQ-sequence

A floorplan is employed to represent the placement of modules in VLSI design. Floorplanning is a key step in the design of VLSI systems because it provides the first estimates of performance and cost including placement and routing. In this paper, we represent the floorplan by an EQ-sequence and show an algorithm for initial global routing based on the EQ-sequence. The aim of our algorithm is to get a minimum chip area and the shortest total length of wires where the longest (critical) wire in every net is reduced to a minimum. The experimental results show that the design of placement and routing in floorplanning can be considered simultaneously by our algorithm, the efficiency of automatic layout in VLSI can be raised.