Realistic fault models and test procedure for multi-port SRAMs

Author

Hamdioui, Said ; van de Goor, A.J. ; Eastwick, David ; Rodgers, Mike

Author_Institution

Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands

fYear

2001

fDate

2001

Firstpage

65

Lastpage

72

Abstract

This paper presents realistic fault models for multi-port memories with p ports, based on defect injection and SPICE simulation. The results show that the fault models for p-port memories consist of p classes: single-port faults, two-port faults, ... , p-port faults. In addition, the paper discusses the test procedure for such memories. It shows that the time complexity of the required tests is not exponentially proportional with p, as published by different authors, but it is linear; irrespective of the number of ports the multi-port memory consists of

Keywords

SPICE; SRAM chips; VLSI; computational complexity; fault simulation; integrated circuit testing; integrated memory circuits; logic testing; SPICE simulation; defect injection; functional fault models; multi-port SRAMs; multi-port memories; realistic fault models; test procedure; time complexity; Bridge circuits; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Educational institutions; Interference; Random access memory; SPICE; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945230

Filename

945230