Equivalence checking a 256 MB SDRAM

Author

Napper, Simon ; Yang, Dian

Author_Institution

InnoLogic Syst. Inc, San Jose, CA, USA

fYear

2001

fDate

2001

Firstpage

85

Lastpage

89

Abstract

This paper outlines how symbolic simulation was used to verify both data and sequence integrity in a 256 MB SDRAM. The initial step is to examine the underlying equivalence-checking engine and then explain how it is applied to SDRAM verification. SDRAM verification is interesting in that it captures both memory and sequence verification. The data integrity verification is valid for any type of memory structure and the sequence integrity can be extended to many types of sequenced machines

Keywords

DRAM chips; circuit simulation; data integrity; formal verification; integrated circuit testing; logic testing; sequences; symbol manipulation; SDRAM verification; custom equivalence checking; data integrity; equivalence-checking engine; formal verification; memory structure; memory verification; sequence integrity; sequence verification; symbolic simulation; symbolic simulation equivalence checking; synchronous DRAM; Acoustic propagation; Circuit simulation; Electronic design automation and methodology; Engines; Formal verification; Logic; SDRAM; SPICE; Switches; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945234

Filename

945234