Testing carry logic modules of SRAM-based FPGAs

Author

Sun, Xiaoling ; Xu, Jian ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2001

fDate

2001

Firstpage

91

Lastpage

98

Abstract

The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by the integrity of all its components. It has been found that the minimum numbers of CLM test configurations (TCs) under single stuck-at, multiple stuck-at, and universal fault models are six, seven and eight respectively. A set of selection criteria was proposed to obtain the "best" of eight TCs, each contains a subset of six and seven TCs for the two stuck-at fault models. These CLM TCs can be extended to include the test of the whole CLB

Keywords

carry logic; controllability; fault simulation; field programmable gate arrays; integrated circuit testing; logic testing; observability; random-access storage; CLM integrity; SRAM-based FPGAs; Xilinx XC4000; carry logic module testing; configurable logic block; field programmable gate array; multiple stuck-at fault model; selection criteria; single stuck-at fault model; testability; universal fault models; Built-in self-test; Circuit faults; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic devices; Logic testing; Multiplexing; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, IEEE International Workshop on, 2001.

Conference_Location

San Jose, CA

Print_ISBN

0-7695-1242-9

Type

conf

DOI

10.1109/MTDT.2001.945235

Filename

945235