Low voltage and low leakage flip-flops based on transmission gate in nanometer CMOS processes

Author

Xiaoying Yu ; Xiaoyan Luo ; Jianping Hu

Author_Institution

Fac. of Inf. Sci. & Technol, Ningbo Univ., Ningbo, China

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

Scaling supply voltage is an effective technique to achieve low energy delay product (EDP). This paper presents low voltage and low leakage flip-flops using dual-threshold CMOS (low threshold and ultra high threshold) to reduce leakage power. Four flip-flops based on transmission gates are investigated from 0.3V to 1.1V in term of EDP. The simulation results show that lowering supply voltage is advantageous, especially in low voltage region (800mv-900mv) at 45nm CMOS technology, which yields the best EDP. The proposed flip-flop achieves considerable leakage reductions.

Keywords

CMOS digital integrated circuits; flip-flops; dual-threshold CMOS; leakage reductions; low energy delay product; low leakage flip-flops; low voltage flip-flops; low voltage region; nanometer CMOS processes; size 45 nm; supply voltage scaling; transmission gate; voltage 0.3 V to 1.1 V; CMOS integrated circuits; CMOS technology; MOS devices; Transistors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026654

Filename

6026654