Interference-robust serial dual-path threshold referenced architecture for PN acquisition

We investigate the performance of serial PN acquisition architectures in the presence of noise and interference. In particular, the performance of a low complexity serial correlator with constant threshold (CT) and a dual-path threshold referenced (DPTR) architecture are studied. Using an AWGN channel model, analytical expressions have been derived for the probability of false alarm, the probability of detect, and the mean acquisition time. Simulations have been performed to verify the theoretical analysis. We show that for a practical range of chip-to-noise ratios (CNR), the basic serial correlator yields comparable performance to the dual-path threshold reference method. However, the performance gain of the DPTR architecture is up to 3 dB in CNR or 4 times lower in the mean acquisition time when interference is present in the channel, making this architecture suitable for interference limited environments