Voltage-mode loser/winner-take-all circuits

In this paper, a general architecture for analog implementation of LTA/WTA and other rank-order circuits is presented. This architecture composed of a differential amplifier with merged n-inputs and a MCSAL circuit to choose the desired input. The advantages of the proposed structure are simplicity, high operating frequency, very high resolution, very low supply voltage requirements, very low output resistance, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. Post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35μm CMOS process technology. The total power dissipation of proposed circuits is about 110μW. Also, the total active area is about 550μm² for five-input proposed circuits, and would be negligibly increased for each extra input.