Title :
A scalable I/O architecture for wide I/O DRAM
Author :
Harvard, Q. ; Baker, R. Jacob
Author_Institution :
Dept. of Electr. & Comput. Eng., Boise State Univ., Boise, ID, USA
Abstract :
A 4 Gb DRAM architecture utilizing a scalable number of data pins is proposed. The architecture does not impact chip size and does not require additional metal layers. The 4 Gb DRAM measure 68.88 mm2 and achieves an array efficiency of 59.9%. This was accomplished by using a split bank, edge I/O interface, central row, and central column structures. The architecture coincides with the chip size and array efficiency measurements predicted by the ITRS for a 40 nm 2012 production DRAM architecture.
Keywords :
DRAM chips; DRAM architecture; central column; central row; edge I/O interface; efficiency 59.9 percent; scalable I/O architecture; split bank; storage capacity 4 Gbit; wide I/O DRAM; Fires; Random access memory; Routing;
Conference_Titel :
Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on
Conference_Location :
Seoul
Print_ISBN :
978-1-61284-856-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2011.6026682
