A power-efficient polyphase sharpened CIC filter for sigma-delta ADCs

Author

Karnati, N.R. ; Kye-Shin Lee ; Carletta, Joan ; Veillette, R.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Akron, Akron, OH, USA

fYear

2011

fDate

7-10 Aug. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a power-efficient poly-phase sharpened CIC filter for sigma-delta ADCs. In this scheme, by using a cascade of CIC filter and SCIC filter with proper optimization of the two-stage decimation structure, the power consumption can be considerably reduced compared to conventional SCIC filter architectures. Furthermore, poly-phase implementations for both the CIC and SCIC filter sections are used to further reduce the power. The proposed filter is designed with CMOS 1 μm technology, where the lowest power consumption is achieved among similar filter architectures.

Keywords

CMOS integrated circuits; cascade networks; circuit optimisation; comb filters; sigma-delta modulation; CMOS technology; SCIC filter; cascaded integrator-comb filter; optimization; power consumption; power-efficient polyphase sharpened CIC filter; sigma-delta ADC; size 1 mum; two-stage decimation structure; CMOS integrated circuits; Measurement; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2011 IEEE 54th International Midwest Symposium on

Conference_Location

Seoul

ISSN

1548-3746

Print_ISBN

978-1-61284-856-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2011.6026689

Filename

6026689