A study of a high bandwidth and low latency interconnection network in PIE64

Author

Takahashi, Eiichi ; Koike, Hanpei ; Tanaka, Hidehiko

Author_Institution

Dept. of Electr. Eng., Tokyo Univ., Japan

fYear

1991

fDate

9-10 May 1991

Firstpage

5

Abstract

PIE64 is a parallel inference machine. The goal is fast execution of large-scale knowledge processing. Generally speaking, an interconnection network (IN) is one of the keys to designing a parallel machine and affects a total system architecture. The IN of PIE64 is designed with the aim of maximizing its performance. A discussion is presented of the IN suitable for PIE64, and an IN with circuit switching, nonbuffering, multistage, dynamic load balancing support, and duplicated network is proposed. Its hardware implementation is considered, and the assembling process is described. Electrical characteristics are also described

Keywords

circuit switching; inference mechanisms; multiprocessor interconnection networks; parallel architectures; PIE64; assembling process; circuit switching; dynamic load balancing support; hardware implementation; high-bandwidth low-latency interconnection network; multistage network)); nonbuffering; parallel inference machine; Assembly; Bandwidth; Delay; Hardware; Intelligent networks; Large-scale systems; Load management; Multiprocessor interconnection networks; Parallel machines; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1991., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-87942-638-1

Type

conf

DOI

10.1109/PACRIM.1991.160667

Filename

160667