DocumentCode
3410176
Title
How an “evolving” fault model improves the behavioral test generation
Author
Buonanno, G. ; Ferrandi, F. ; Ferrandi, L. ; Fummi, F. ; Sciuto, D.
Author_Institution
Dipt. di Elettronica, Politecnico di Milano, Italy
fYear
1997
fDate
13-15 Mar 1997
Firstpage
124
Lastpage
129
Abstract
By considering test costs at the behavioral level, test problems can be pointed out during the first phases of the design flow. Thus, in case either some testability problems are identified or the size (and hence the cost) of the test set results to be too high, the designer or the high level synthesis tool can modify the circuit to reduce such testability problems. The main problem is the correspondence between the behavioral and RT or gate level fault models. To overcome such limitation, the paper presents a design flow based on the behavioral fault model modification (“evolution”) depending on the actual RTL implementation
Keywords
VLSI; automatic test software; design for testability; high level synthesis; integrated circuit testing; logic testing; RT level fault model; RTL implementation; behavioral fault model modification; behavioral level; behavioral test generation; gate level fault model; high level synthesis tool; test costs; testability problems; Character generation; Circuit faults; Circuit testing; Complexity theory; Costs; High level synthesis; Logic design; Logic testing; System testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1997. Proceedings. Seventh Great Lakes Symposium on
Conference_Location
Urbana-Champaign, IL
ISSN
1066-1395
Print_ISBN
0-8186-7904-2
Type
conf
DOI
10.1109/GLSV.1997.580515
Filename
580515
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