Title :
Scaling of stack effect and its application for leakage reduction
Author :
Narendra, Siva ; Borkar, Shekhar ; De, Vivek ; Antoniadis, D. ; Chandrakasan, Anantha
Author_Institution :
Microsystems Technol. Lab., MIT, Cambridge, MA, USA
Abstract :
Technology scaling demands a decrease in both Vdd and V t to sustain historical delay reduction, while restraining active power dissipation. Scaling of Vt however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. In this paper we present a model that predicts the scaling nature of this leakage reduction effect. Device measurements are presented to prove the model´s accuracy. Use of stack effect for leakage reduction and other implications of this effect are discussed
Keywords :
CMOS integrated circuits; delays; integrated circuit design; integrated circuit measurement; integrated circuit modelling; leakage currents; low-power electronics; statistical analysis; CMOS technology; active power dissipation; historical delay reduction; leakage current; leakage reduction; model; off devices; stack effect; statistical device measurements; sub-threshold leakage power; technology scaling; total dissipated power; CMOS technology; Delay effects; Laboratories; Leakage current; Microprocessors; Permission; Power dissipation; Predictive models; Semiconductor device modeling; Stacking;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945400
