DocumentCode :
3410476
Title :
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in microprocessors
Author :
Hsu, Chung-Hsing ; Kremer, Ulrich ; Hsiao, Michael
Author_Institution :
Dept. of Comput. Sci., Rutgers Univ., NJ, USA
fYear :
2001
fDate :
2001
Firstpage :
275
Lastpage :
278
Abstract :
Dynamic voltage and frequency scaling of the CPU has been identified as one of the most effective ways to reduce energy consumption of a program. This paper discusses a compilation strategy that identifies scaling opportunities without significant overall performance penalty. Simulation results show CPU energy savings of 3.97%-23.75% for the SPECfp95 benchmark suite with a performance penalty of at most 2.53%
Keywords :
low-power electronics; microprocessor chips; processor scheduling; program compilers; CPU energy savings; compilation strategy; compiler-directed dynamic scheduling; dynamic voltage/frequency scheduling; energy reduction; microprocessors; Clocks; Computer architecture; Dynamic compiler; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Frequency; Microprocessors; Processor scheduling; Program processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
Type :
conf
DOI :
10.1109/LPE.2001.945416
Filename :
945416
Link To Document :
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