Synthesis of low-leakage PD-SOI circuits with body-biasing

Author

Casu, Mario R. ; Piccinini, Gianluca

Author_Institution

Politecnico di Torino, Italy

fYear

2001

fDate

2001

Firstpage

287

Lastpage

290

Abstract

In this work we propose a methodology for the reduction of leakage power dissipation through the use of smart body contacts in a partially depleted Silicon-on-Insulator (PD-SOI) technology. Reverse body biasing is used to increase threshold voltage in standby while in active mode PD-SOI gates switch with nominal Vth. As opposed to standard dual-Vth techniques used in CMOS bulk circuits, PD-SOI enables the application of body-bias to all gates included those in critical paths without delay penalties. Results are reported for the ISCAS85 combinational benchmarks

Keywords

CMOS integrated circuits; integrated circuit design; leakage currents; low-power electronics; silicon-on-insulator; CMOS IC; PD-SOI circuit synthesis; active mode; body biasing; combinational logic circuit; leakage power dissipation; low-power design; partially depleted silicon-on-insulator technology; reverse body biasing; smart body contact; standby mode; threshold voltage; CMOS logic circuits; CMOS technology; Circuit synthesis; Delay; MOSFETs; Power supplies; Silicon on insulator technology; Subthreshold current; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, International Symposium on, 2001.

Conference_Location

Huntington Beach, CA

Print_ISBN

1-58113-371-5

Type

conf

DOI

10.1109/LPE.2001.945419

Filename

945419