Modular design of communication node prototypes

A hardware rapid-prototyping system has been developed in order to experiment with different communication networks for massively parallel systems. Processing and communication in such systems should be kept well separated both at abstract description and implementation levels. This results in a distinct physical implementation of processing elements (PE), relevant to computing tasks, and nodes for internode and node-PE communication. Rationales of this are briefly exposed. The main topic is the design of a macro library for FPGA devices. A proper combination of library blocks and some user-defined combinational logic blocks makes it possible to implement the chosen network topology. High communication bandwidth can be achieved by subdividing the node workload among concurrent blocks. As an example, the design of a node for a (4,3)-WK recursive network-issuing wormhole point-to-point and broadcasting-is presented