DocumentCode
3410524
Title
Three-level SNPC commutation cell: Features and control
Author
Floricau, D. ; Floricau, E. ; Gateau, G.
Author_Institution
Fac. of Electr. Eng., Politeh. Univ. of Bucharest, Bucharest
fYear
2008
fDate
June 30 2008-July 2 2008
Firstpage
44
Lastpage
49
Abstract
The unequal distribution of losses among the semiconductors represents one major disadvantage for 3L-SC (stacked cells) and 3L-NPC (neutral point clamped) commutation cells. The paper studies the loss distribution problem for 3L-SC and 3L-NPC topologies and proposes the 3L-SNPC (stacked NPC) commutation cell to overcome this drawback. A new PWM strategy for 3L-SNPC commutation cell is also presented. It has numerous advantages: (a) natural doubling of the apparent switching frequency without using the flying-capacitor concept, (b) dead times do not influence the operating mode at 50% of the duty cycle, (c) operating at both high and small switching frequencies without structural modifications and (d) better balancing of loss distribution in switches. The PSIM simulation and experimental results are shown in order to validate the proposed PWM strategy and the analysis of the switching states.
Keywords
PWM power convertors; capacitors; commutation; switching convertors; PSIM simulation; PWM strategy; apparent switching frequency; flying-capacitor concept; neutral point clamped commutation cells; stacked cells; three-level SNPC commutation cell; Capacitors; Clamps; Pulse width modulation; Semiconductor diodes; Switches; Switching converters; Switching frequency; Temperature; Topology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics, 2008. ISIE 2008. IEEE International Symposium on
Conference_Location
Cambridge
Print_ISBN
978-1-4244-1665-3
Electronic_ISBN
978-1-4244-1666-0
Type
conf
DOI
10.1109/ISIE.2008.4677034
Filename
4677034
Link To Document