• DocumentCode
    3410641
  • Title

    Optimizing bias-circuit design of cascode operational amplifier for wide dynamic range operations

  • Author

    Fukumoto, Takeshi ; Okada, Hiroyuki ; Nakamura, Kazuyuki

  • Author_Institution
    Silicon Syst. Res. Labs., NEC Corp., Kanagawa, Japan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    305
  • Lastpage
    309
  • Abstract
    Proposed here is a bias circuit for use in a cascode operational amplifier to provide a wide output dynamic range. The bias circuit has been designed so that the drain-source voltage of each MOS transistor used in the gain stage is minimized to Vdsat automatically, making it possible to widen the output dynamic range
  • Keywords
    CMOS analogue integrated circuits; circuit optimisation; low-power electronics; operational amplifiers; MOS transistor; bias circuit design optimization; cascode operational amplifier; drain-source voltage; dynamic range; low-voltage CMOS analog integrated circuit; CMOS technology; Circuits; Design optimization; Dynamic range; MOSFETs; Mirrors; Operational amplifiers; Permission; Silicon; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Low Power Electronics and Design, International Symposium on, 2001.
  • Conference_Location
    Huntington Beach, CA
  • Print_ISBN
    1-58113-371-5
  • Type

    conf

  • DOI
    10.1109/LPE.2001.945423
  • Filename
    945423
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3410641