Title :
A study of charge neutralization method during high current ion implantation for ultra thin gate dielectrics
Author :
Niwayama, Masatsugu ; Kubo, Hiroshi ; Yoneda, K.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto
Abstract :
Ultra thin gate oxide breakdown due to excess electrons supplied by charge neutralization system such as plasma flood system (PFS) is discussed. For the ultra thin gate oxide below 5 nm, the oxide breakdown due to not only positive charge build-up by ions but also negative charge build-up by PFS becomes noticeable. The maximum energy of electrons from PFS dominates the oxide breakdown instead of total electron flux. For the 3.5 nm gate oxide, maximum electron energy should not exceed 9 eV to suppress the breakdown. For the ultra thin gate dielectrics, the energy control of electron is most important to suppress the oxide breakdown by excess electrons from PFS
Keywords :
CMOS integrated circuits; MOS capacitors; electric breakdown; integrated circuit reliability; ion implantation; CMOS devices; antenna MOS capacitors; charge neutralization method; electron energy control; excess electrons; high current ion implantation; maximum electron energy; negative charge build-up; plasma flood system; positive charge build-up by ions; total electron flux; ultra thin gate dielectrics; ultra thin gate oxide breakdown; Breakdown voltage; Design for quality; Electric breakdown; Electrodes; Electron beams; Floods; Ion implantation; MOS capacitors; Plasma applications; Plasma immersion ion implantation;
Conference_Titel :
Ion Implantation Technology Proceedings, 1998 International Conference on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4538-X
DOI :
10.1109/IIT.1999.812187