Title :
Clocking strategies and scannable latches for low power applications
Author :
Zyuban, V. ; Meltzer, D.
Author_Institution :
Div. of Res., IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This paper covers a range of issues in the design of clocking schemes for low-power applications. First we revisit, extend and improve the power-performance optimization methodology for latches, attempting to make it more formal and comprehensive. The data switching factor and the glitching activity are taken into consideration, using a formal analytical approach, then a notion of energy-efficient family of configurations is introduced to make the comparison of different latch styles in the power-performance space more fair, also the power of the clock distribution is taken into account. Practical issues of building a low overhead scan mechanism are considered, and the power overhead of the scannable design is analyzed. A low-power LSSD extension to single-phase latches is proposed, and results of a comparative study of LSSD-scannable latches are shown, supported by experimental data measured on a 0.18 μm test chip
Keywords :
circuit optimisation; flip-flops; logic design; low-power electronics; synchronisation; timing; clock distribution; clocking schemes; clocking strategies; data switching factor; energy-efficient family; glitching activity; low overhead scan mechanism; low power applications; low-power LSSD extension; power-performance optimization methodology; scannable design; scannable latches; single-phase latches; Buildings; Clocks; Delay; Energy efficiency; Measurement; Optimization methods; Research and development; Scalability; Testing; Voltage;
Conference_Titel :
Low Power Electronics and Design, International Symposium on, 2001.
Conference_Location :
Huntington Beach, CA
Print_ISBN :
1-58113-371-5
DOI :
10.1109/LPE.2001.945430
