An enhanced frequency synthesizer using an analog dual input accumulator

In this paper we propose an implementation of a PLL based frequency synthesizer, in which, we have replaced the conventional phase frequency detector and the dividers (programmable counters) with an analog Dual Input Phase Accumulator (DIPA), consisting of four switches, two capacitors, an integrator and a high-accuracy, low-speed D/A converter. The main feature of the DIPA is that the two input frequencies are not required to be normalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output frequency of the synthesizer, are applied directly. The DIPA samples and normalizes their phases at very high rates and calculates their phase difference, producing an output consisting of a DC component proportional to their phase difference and harmonics of the two input high frequencies. These harmonics are high frequencies and can easily be rejected by a wide bandwidth filter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs nearby the output frequency. The resolution of the DIPA based synthesizer does not affect the convergence speed of the synthesizer, affected by the lower of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of ±2π that governs the conventional phase detectors. Thus, the proposed frequency synthesizer based on the analog DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast convergence rate