Title :
High performance branch prediction
Author :
Guy, Buford Mason, III ; Haggard, Roger L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN, USA
fDate :
31 Mar-2 Apr 1996
Abstract :
Today´s advanced architectures increasingly rely on accurate instruction fetch and branch prediction to maintain optimum pipeline performance. In this paper, dynamic branch prediction techniques are investigated and methods to increase branch prediction accuracy are explored. A result of this analysis has been the development of several dynamic branch prediction architectures that combine promising aspects of accurate branch prediction methods currently implemented. The objective of this research was to provide an advanced high performance branch prediction architecture that can easily be incorporated into existing architectures without instruction set modification. Development of a hybrid branch prediction architecture that uses both global and local branch histories is presented and shown to have significant performance advantages. Several branch architectures are presented for performance
Keywords :
instruction sets; pipeline processing; reduced instruction set computing; remote procedure calls; resource allocation; accurate instruction fetch; advanced architectures; branch prediction accuracy; dynamic branch prediction techniques; global branch histories; high performance branch prediction; local branch histories; optimum pipeline performance; Accuracy; Clocks; Computer aided instruction; Computer architecture; Decoding; Hardware; History; Maintenance engineering; Parallel processing; Pipelines;
Conference_Titel :
System Theory, 1996., Proceedings of the Twenty-Eighth Southeastern Symposium on
Conference_Location :
Baton Rouge, LA
Print_ISBN :
0-8186-7352-4
DOI :
10.1109/SSST.1996.493550