Digit-serial design of a wave digital filter

A digit-serial design of a third order wave digital filter using a mixture of static and TSPC logic styles is presented. A fixed-coefficient digit-serial multiplier has been developed and used in the design. The design offers a small area, large density, and low power consumption comparing with previously published results. Digit-serial computation style is discussed and different computational styles are compared with regard to area, speed, and power consumption