Title :
A power optimized 14-bit SC ΔΣ modulator for ADSL CO applications
Author :
Gaggl, Richard ; Wiesbauer, Andreas
Author_Institution :
Infineon Technol. Austria AG, Villach, Austria
Abstract :
A switched-capacitor multi-bit ΔΣ ADC including a reference-voltage buffer is implemented in 0.13 μm CMOS. The single loop 3 b modulator features 14 b and 13 b dynamic range over 276 kHz and 1.1 MHz signal bandwidths, respectively. Clocked at 105 MHz, the ADC core consumes 8 mW from a 1.5 V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; circuit optimisation; delta-sigma modulation; digital subscriber lines; integrated circuit design; low-power electronics; reference circuits; switched capacitor networks; 0.13 micron; 1.1 MHz; 1.5 V; 105 MHz; 13 bit; 14 bit; 276 kHz; 3 bit; 8 mW; ADC core consumption; ADSL CO applications; CMOS; dynamic range; power optimized SC delta-sigma modulator; reference-voltage buffer; signal bandwidths; single loop modulator; switched-capacitor multi-bit ΔΣ ADC; Bandwidth; Circuit noise; Circuit topology; DSL; Delta modulation; Feedforward systems; Multi-stage noise shaping; Noise shaping; Signal resolution; Silicon;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332604
