DocumentCode
3411620
Title
A mirror image free two-path bandpass ΣΔ modulator with 72 dB SNR and 86 dB SFDR
Author
Ying, Feng ; Maloberti, Franco
Author_Institution
High Performance Analog, Texas Instruments, Dallas, TX, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
84
Abstract
A cross-coupled two-path ΣΔ architecture generates transmission zeros at 1/3 of the clock frequency, thereby achieving a mirror image free response. The chip uses 0.18 μm CMOS technology and is clocked at 2×60 MHz with a 40 MHz IF. The modulator achieves an 86 dB SFDR with a 2.5 MHz bandwidth and consumes 150 mW from a 1.8 V supply.
Keywords
CMOS integrated circuits; band-pass filters; clocks; integrated circuit measurement; integrated circuit noise; low-power electronics; sigma-delta modulation; 1.8 V; 120 MHz; 150 mW; 2.5 MHz; 40 MHz; 60 MHz; CMOS technology; SFDR; SNR; chip clock; clock frequency; cross-coupled two-path sigma-delta architecture; mirror image free response; mirror image free two-path bandpass ΣΔ modulator; modulator bandwidth; transmission zeros; Circuit noise; Clocks; Delta modulation; Frequency; Mirrors; Multi-stage noise shaping; Noise shaping; Phase modulation; Quantization; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332605
Filename
1332605
Link To Document