A design reliability methodology for CMOS VLSI circuits

As integrated circuits become more complex, ensuring product reliability in a timely and efficient manner is becoming more challenging. Historically, the focus has been to manage reliability through robust manufacturing processes. This approach does not address reliability issues associated with IC design. ´Design-for-Reliability´ (DFR) methodologies should be incorporated into chip design flow and CAD tools, to meet the submicron challenge. At Cadence Spectrum Design, a set of practical DFR tools and procedures have been developed and deployed to realistically manage product reliability throughout the design phase of a VLSI circuit. These procedures manage wear-out concerns through verifying compliance of every node with all the reliability design rules. Random failures (bottom of the bathtub curve) are addressed by analyzing the interaction between design and random process defects in order to determine a failure rate. Finally, infant mortality concerns are managed by insuring that the library is ´robust´, by verifying the validity of test and/or burn-in screens.