The space efficient redundant array

Reliable processor arrays are required to implement many critical, real-time signal processing applications. The interconnected finite state machine model (IFSMM) was used to design two reconfigurable arrays. The distributed interstitial redundancy array (DIRA) uses distributed control with spares placed between processors in the array. The space efficient redundant array (SERA) improves the approach of the DIRA by more efficiently using spares to cover the processor array. In addition, the SERA uses a switching approach with improved spare placement for better VLSI layout. These arrays provide reliable operation, as well as the speed necessary for numerically intensive algorithms.