Detection and measurement of hot carrier degradation associated with asymmetric p-channel transistors

Control and monitoring of the manufacturing process is essential in the production of reliable devices. A recent experience involving the LDD implant of a 0.91-/spl mu/m CMOS process resulted in asymmetric p-channel transistors with spatially dependent hot carrier performance. This event is especially significant because the monitoring in place could have easily missed the degradation in reliability due to the layout dependence of the test structures. This paper presents some of the typical methods used to monitor hot carrier reliability in production and documents the specific event and symptoms caused by the failure of the implanter to properly sense wafer position. This intermittent failure resulted in transistors with an asymmetric source/drain profile. Standard measurements of Vt, Isub and other transistor parameters indicated normal performance for some layouts and severe hot carrier degradation and Vt shifts when measured in other orientations.