Efficient Implementation and Performance Enhancement of the Time-Varying Phase Trellis in CPM

A CPM modulator can be decomposed into a recursive encoder followed by a memoryless mapper. For modulation indices of the form h=K/P with an odd K, the encoder generates a time-varying phase trellis with 2PM^L-1 states. For symmetric and analytically tractable premodulation filters, like GMSK, this time-varying trellis can be implemented efficiently in VLSI, allowing for very low storage requirements and high data rates at the output of the digital circuit. This paper demonstrates the modification of the transfer function matrix of such a time-varying trellis in order to precode the data bits, eliminate double errors and/or allow for an encoder state-independent trellis termination. In addition, a PM^L-1 state MAP decoder is proven to be optimum for this time-varying trellis. Employing a time-varying CPM trellis at the transmitter thus allows for simplified modulator structures with no increase in the receiver complexity