High-level delay estimation technique for porting C-based applications on FPGA

Rapid area-time estimation is an instrumental step for efficient design exploration of FPGA-based implementations. In this paper, we address the issue of high-level delay estimation for porting C-based applications onto FPGA. In particular, we present a framework which incorporates a compiler to generate optimized high-level IR (intermediate representation) of the C-applications and an estimation model that is based on an architecture template with application-specific heterogeneous functional units. In order to accurately predict the post place and route delay of the design, the proposed estimation strategy performs a simplified floor-planning process. This leads to more accurate interconnect delay estimation, which is then combined with the pre-characterized delay parameters of the components. Experimental results based on a set of embedded functions show that the proposed estimation technique can achieve comparable results with synthesis results from a commercial FPGA tool in significantly shorter amount of time. In particular, the proposed method has an average error of only 4% with a maximum error of 10%. In addition, the proposed method leads to more consistent estimation results when compared to the Xilinx synthesis tool and to a naive approach that only employs pre-characterized parameters in the estimation model.