Title :
3D interconnection and packaging: impending reality or still a dream?
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
Traditional interconnect schemes are basically two-dimensional. It has long been a dream for system designers to be able to combine multiple integrated circuits by connecting them in the third dimension. Three approaches to the 3D interconnect problem are described: system in a package (3D-SiP), system on a chip (3D-SoC) and 3D integrated circuits (3D-IC).
Keywords :
CMOS integrated circuits; chip scale packaging; integrated circuit interconnections; system-on-chip; 3D integrated circuits; 3D interconnection; 3D packaging; CMOS die; electrical integrity; enabling technologies; heterogeneous system integration; multiple integrated circuits; system design; system in a package; system on a chip; Energy consumption; Integrated circuit interconnections; Integrated circuit packaging; Integrated circuit technology; Isolation technology; Power system interconnection; Routing; Stacking; Three-dimensional integrated circuits; Wafer bonding;
Conference_Titel :
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
Print_ISBN :
0-7803-8267-6
DOI :
10.1109/ISSCC.2004.1332632
