DocumentCode
3412147
Title
Electronic alignment for proximity communication
Author
Drost, Robert ; Ho, Ron ; Hopkins, Debbie ; Sutherland, I.
Author_Institution
Sun MicroSysterms Inc., Mountain View, CA, USA
fYear
2004
fDate
15-19 Feb. 2004
Firstpage
144
Abstract
This work presents an electronic alignment mechanism for capacitively-coupled proximity communication. On an experimental chip, position offsets of up to +/-100μm are electrically corrected to within 6.25μm. A 0.35μm experimental CMOS chip communicates at 1.35Gb/s with a BER ≤10-10.
Keywords
CMOS integrated circuits; data communication equipment; integrated circuit interconnections; multiplexing equipment; switching circuits; CMOS chip; capacitive coupling; capacitively-coupled proximity communication; chip misalignment; electronic alignment mechanism; multiplexing; on-chip alignment structure; position offsets; random bit patterns; residual integer misalignment; switching circuits; two-dimensional multiplexer; Assembly; Capacitance; Capacitors; Coupling circuits; Glass; Multiplexing; Sun; Switching circuits; Thermal expansion; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
ISSN
0193-6530
Print_ISBN
0-7803-8267-6
Type
conf
DOI
10.1109/ISSCC.2004.1332635
Filename
1332635
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