• DocumentCode
    3412280
  • Title

    Mixed body-bias techniques with fixed Vt and Ids generation circuits

  • Author

    Sumita, M. ; Sakiyama, S. ; Kinoshita, Moto ; Araki, Yuichi ; Ikeda, Yasuhiro ; Fukuoka, Kazuki

  • Author_Institution
    Matsushita Electr. Ind., Nagaokakyo, Japan
  • fYear
    2004
  • fDate
    15-19 Feb. 2004
  • Firstpage
    158
  • Abstract
    In sub-1V CMOS VLSIs, body-bias generation circuits are proposed in which Ids,, and Vt, of PMOS/NMOS are always fixed. The mixed body bias techniques result in positive temperature dependence of the delay, an 85% reduction of the delay variation, and a 75% improvement in the power consumption of an SRAM on a mobile processor.
  • Keywords
    CMOS logic circuits; CMOS memory circuits; SRAM chips; VLSI; integrated circuit design; low-power electronics; microprocessor chips; CMOS VLSI; SRAM; body-bias generation circuits; correlation diagram; delay variation; domino circuits; low power; mixed body-bias techniques; mobile processor; positive temperature dependence; power consumption; readout circuit; CMOS process; CMOS technology; Circuit testing; Intrusion detection; MOS devices; Radio frequency; Random access memory; Semiconductor device measurement; Temperature; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-8267-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.2004.1332642
  • Filename
    1332642
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3412280