A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

Author

Watanabe, K. ; Koyama, Akio ; Harada, Tatsuya ; Aida, Toshiaki ; Ito, Akinori ; Murata, Takafumi ; Yoshioka, Hiroki ; Sonehara, Makoto ; Yamashita, Hiromasa ; Ishikawa, Kenji ; Ito, Minora ; Shiramizu, N. ; Nakamura, T. ; Ohhata, Kenichi ; Arakawa, Fumio

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2004

fDate

15-19 Feb. 2004

Firstpage

166

Abstract

A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18μm BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV_PP single-ended with a BER <10^-12.

Keywords

BiCMOS integrated circuits; demultiplexing equipment; integrated circuit noise; jitter; millimetre wave oscillators; multiplexing equipment; optical communication equipment; voltage-controlled oscillators; 39.8 to 43 Gbit/s; BiCMOS process; Integrated VCO; MUX/DEMUX chipset; OC-768 communication systems; dual-PLL architecture; full-rate operation; high-sensitivity DEMUX; industry-standard chipset; input sensitivity performance; jitter tolerance; low-jitter MUX; on-chip VCO; output jitter; phase-interpolator-based data recovery; power reduction; Bandwidth; BiCMOS integrated circuits; Clocks; Filters; Frequency; Indium tin oxide; Jitter; Phase locked loops; Power dissipation; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International

ISSN

0193-6530

Print_ISBN

0-7803-8267-6

Type

conf

DOI

10.1109/ISSCC.2004.1332646

Filename

1332646