An effective apparatus for at-speed self-testing

Author

Li, Xiaowei ; Cheung, Paul Y S

Author_Institution

Dept. of Comput. Sci. & Technol., Beijing Univ., China

Volume

2

fYear

1999

fDate

1999

Firstpage

844

Abstract

This paper presents a loop-based BIST scheme for at-speed testing. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed. Based on it, an approach to design and efficiently implement the proposed BIST scheme has been developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach

Keywords

automatic test pattern generation; built-in self test; directed graphs; fault diagnosis; finite state machines; integrated circuit testing; logic testing; sequential circuits; ATPG; at-speed self-testing; autonomous FSM; benchmark circuits; delay testing; design approach; directed graph; faulty dynamic logic; input separation; loop-based BIST scheme; multiple input shift register; operation modes; response compression; sequential circuits; state-transition-graph; stuck at test; topological properties; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Delay; Integrated circuit testing; Logic testing; Performance evaluation; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference, 1999. IMTC/99. Proceedings of the 16th IEEE

Conference_Location

Venice

ISSN

1091-5281

Print_ISBN

0-7803-5276-9

Type

conf

DOI

10.1109/IMTC.1999.776984

Filename

776984