Title :
Characteristics of interconnect delay in 0.5 micron CMOS
Author_Institution :
Motorola Inc., Chandler, AZ, USA
Abstract :
Accurate analysis of the interconnect is imperative in contemporary sub-micron geometry circuits. The drive characteristics of the driving transistor play a significant role in the response of the interconnect. This paper presents a detailed analysis of a capacitively loaded distributed RLC system driven by a transistor. Using an analytic model the performance of the interconnect will be characterized with respect to design and technology parameters of a CMOS process technology with Leff=0.45 micron
Keywords :
CMOS integrated circuits; delays; distributed parameter networks; integrated circuit interconnections; integrated circuit modelling; 0.5 micron; CMOS process technology; analytic model; capacitive load; design; distributed RLC system; driving transistor; interconnect delay; sub-micron circuits; CMOS technology; Delay effects; Distributed parameter circuits; Geometry; Integrated circuit interconnections; Performance analysis; Propagation delay; RLC circuits; Semiconductor device modeling; Wire;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580672
