Single copy vs. multiple copies cache coherence protocols for hierarchical bus multiprocessors

Reducing memory access time is a very important factor in increasing the performance of multiprocessors. This could be achieved by using caches to hide the memory latency. In multiprocessors, caches introduce another problem, namely the cache coherence problem. In this paper, we investigate single-copy cache coherence protocols for multiprocessors with a hierarchical bus structure. We introduce two different single-copy cache coherence protocols and a third protocol that allows a limited number of copies in the system. We compare our protocol to some of the well-known multiple-copy cache coherence protocols for hierarchical systems using a synthetic workload model