Techniques for reducing switching noise in high speed digital systems

Author

Gong, Shaohg ; Hentzell, Hans ; Persson, Sven-Tuve ; Hesselbom, Hjalmar ; Lofstedt, Bo ; Hansen, Magnus

Author_Institution

Ind. Microelectron. Centre, Linkoping, Sweden

fYear

1995

fDate

18-22 Sep 1995

Firstpage

21

Lastpage

24

Abstract

Simultaneous switching noise (SSN) caused by parasitic inductance in the power supply distribution network is a severe problem in high speed digital circuits and systems. The influence of SSN, negligible when rise/fall time is long (>5 ns), becomes an important factor, limiting circuit performance in the sub-nanosecond rise time region. This paper presents simulation results of SSN in high speed digital systems. Technical solutions for reducing SSN in the light of current developments of advanced packaging and assembly technologies are discussed. A quantitative comparison of SSN in digital systems implemented with conventional as well as advanced assembly techniques is given

Keywords

circuit analysis computing; digital integrated circuits; integrated circuit noise; assembly; high speed digital circuits; packaging; parasitic inductance; power supply distribution network; simulation; simultaneous switching noise; sub-nanosecond rise time; Circuit noise; Circuit optimization; Circuit simulation; Digital circuits; Digital systems; Inductance; Noise reduction; Packaging; Power supplies; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580673

Filename

580673