• DocumentCode
    3412592
  • Title

    Development of frequency synthesizer based on DDS+PLL

  • Author

    Xuehua, Mu ; Jinzhang, Wang

  • Author_Institution
    Beijing Leiyin Electron. Technol. Dev. Co., Ltd., Beijing, China
  • Volume
    2
  • fYear
    2011
  • fDate
    24-27 Oct. 2011
  • Firstpage
    1251
  • Lastpage
    1254
  • Abstract
    Phase Locked Loop (PLL) and Direct Digital Frequency synthesis are used widely in the modern frequency synthesis technology. They have their merits and disadvantages respectively. It is feasible to combine the two methods to perform their merits and overcome their disadvantages. The mode of DDS driving PLL is presented to design the frequency synthesizer. The focus of this paper is the hardware implementation, including system elements, key unit circuit design, and phase noise performance of this system is analyzed. Finally, experimental results, which satisfy the design requirements, are introduced.
  • Keywords
    direct digital synthesis; phase locked loops; phase noise; DDS+PLL; direct digital frequency synthesis technology; frequency synthesizer; key unit circuit design; phase locked loop; phase noise performance; Bandwidth; Frequency synthesizers; Phase locked loops; Phase noise; Radiation detectors; Voltage-controlled oscillators; DDS plus PLL; frequency synthesis; loop filter; phase noise;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radar (Radar), 2011 IEEE CIE International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    978-1-4244-8444-7
  • Type

    conf

  • DOI
    10.1109/CIE-Radar.2011.6159783
  • Filename
    6159783