Digital filter ASIC for NASA deep space radio science receiver

Author

Kowalski, James E. ; Berner, Jeff B.

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

39

Lastpage

42

Abstract

Implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB is described. It uses two decimation by five units and six decimations by two executed by a single decimation by two unit. The six decimations by two consist of six halfband filters, five having 19-taps and one having 51-taps. Use of 16×16 register files for the digital delay lines and programmable coefficients enables implementation in the Vitesse 350 K gate array

Keywords

application specific integrated circuits; digital filters; radio receivers; radiofrequency filters; space communication links; space vehicle electronics; 16 bit; 80 MHz; ASIC; NASA deep space radio science receiver; Vitesse 350K gate array; bandpass ripple; decimation; digital delay lines; digital filter; halfband filters; multi-stage filter; programmable coefficients; register files; Application specific integrated circuits; Band pass filters; Bandwidth; Delay lines; Digital filters; Filtering; Finite impulse response filter; NASA; Receivers; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580677

Filename

580677