Title :
A complete 0.5 μm high performance array family
Author_Institution :
Fujitsu Microelectron. Inc., San Jose, CA, USA
Abstract :
A 3.3 V CMOS gate array and embedded array family with 0.5 μm drawn channel length and three metal layers has been developed for high performance applications. With internal toggle frequency at 600 MHz, this array family can be designed to handle over 100 MHz, and even up to 200 MHz system speed. In addition, high speed I/O´s, tight clock skew control methodology, embedded macros and high performance BGAs are developed to provide designers a complete solution for high speed system designs
Keywords :
CMOS logic circuits; logic arrays; 0.5 micron; 100 to 200 MHz; 3.3 V; BGAs; CMOS gate array; clock skew; embedded macros; high performance family; high speed I/Os; internal toggle frequency; CMOS technology; Character generation; Clocks; Communication system control; Computer applications; Control systems; Electronics packaging; Frequency; Microelectronics; Power supplies;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580680
