• DocumentCode
    3412696
  • Title

    VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder

  • Author

    Janik, Kenneth J. ; Lu, Shih-Lien

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA
  • fYear
    1995
  • fDate
    18-22 Sep 1995
  • Firstpage
    57
  • Lastpage
    59
  • Abstract
    As modern processors´ word lengths increase and clock cycle times get shorter, it becomes more and more important to have basic arithmetic functions which can be used without becoming a bottleneck. The parallel prefix adder has depth O(log n) and area O(n). Since the parallel prefix adder has a regular structure with very limited fan-out, it is ideally suited for use in VLSI applications
  • Keywords
    adders; 32 bit; Kozen formulation; Ladner/Fischer adder; VLSI implementation; parallel prefix adder; Adders; Arithmetic; Bismuth; Clocks; Costs; Delay; Equations; Integrated circuit interconnections; Signal generators; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
  • Conference_Location
    Austin, TX
  • ISSN
    1063-0988
  • Print_ISBN
    0-7803-2707-1
  • Type

    conf

  • DOI
    10.1109/ASIC.1995.580681
  • Filename
    580681
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3412696