VLSI implementation of discrete wavelet transform

Author

Grzeszczak, A. ; Yeap, T.H. ; Panchanathan, S.

Author_Institution

Dept. of Electr. Eng., Ottawa Univ., Ont., Canada

fYear

1995

fDate

18-22 Sep 1995

Firstpage

71

Lastpage

74

Abstract

This paper presents a VLSI implementation of discrete wavelet transform (DWT). The architecture is systolic in nature and performs both high-pass and low-pass coefficient calculations with only one set of multipliers, in contrast to the approaches presented in the literature. The architecture is simple, modular, and cascadable, and has been implemented in VLSI. Experimental results show that real-time coefficient calculation on a 512×512 monochrome video input can be achieved with 1.2 μm technology

Keywords

VLSI; data compression; image coding; multiplying circuits; systolic arrays; transforms; wavelet transforms; 1.2 micron; VLSI implementation; cascadable architecture; discrete wavelet transform; high-pass coefficient calculations; low-pass coefficient calculations; multipliers; systolic architecture; Computer architecture; Discrete cosine transforms; Discrete wavelet transforms; Finite impulse response filter; Image coding; Image processing; Image reconstruction; Very large scale integration; Video compression; Wavelet transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580684

Filename

580684