VHDL code automatic generation for repetitive designs

The introduction of VHDL in ASIC design has radically changed perspectives for HW designers. As a matter of fact ASIC design characteristics are becoming more and more similar to those typical of SW design. So, the application of SW methodologies to HW VHDL design can, in different cases, open unusual possibilities and give great improvement. In this paper a new design approach is described for circuits characterised by a high degree of recurrence in constituting parts, consisting in VHDL code generation starting from high level description in a suitable language