Timed dependence flow graphs, an intermediate form for verified high-level synthesis

Author

Chapman, Richard

Author_Institution

Dept. of Comput. Sci. & Eng., Auburn Univ., AL, USA

fYear

1995

fDate

18-22 Sep 1995

Firstpage

109

Lastpage

112

Abstract

We present timed dependence flow graphs, an intermediate form for high-level synthesis from specifications written in behavioral hardware description languages. Timed dependence flow graphs express data, control, resource access, and timing dependences, and call be constructed in linear time from behavioral VHDL descriptions. We also present a formal execution semantics for timed dependence flow graphs, which we are using in verification of our high-level synthesis tools

Keywords

data flow graphs; formal verification; hardware description languages; high level synthesis; VHDL; behavioral hardware description languages; formal execution semantics; high-level synthesis; timed dependence flow graphs; verification; Computational modeling; Concurrent computing; Delay effects; Flow graphs; Hardware; High level synthesis; Parallel processing; Signal processing; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580693

Filename

580693

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3412850