Title :
Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC
Author :
Ker, Ming-Dou ; Wang, Kuo-Feng ; Joe, Mei-Chu ; Chu, Yuan-Hua ; Wu, Tain-Shun
Author_Institution :
VLSI Design Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
There are one PTLSCR and one NTLSCR devices in parallel with output PMOS and NMOS devices, respectively, to improve ESD robustness of CMOS output buffer in deep submicron CMOS IC´s. PTLSCR (NTLSCR) is merged together with output PMOS (NMOS) device to save layout area for high-density applications. Experimental results show that this proposed CMOS output buffer can sustain up to 4000 V (700 V) Human-Body-Mode (Machine-Mode) ESD stresses with small layout area in a 0.6-μm CMOS technology with LDD and polycide processes
Keywords :
CMOS integrated circuits; application specific integrated circuits; buffer circuits; electrostatic discharge; integrated circuit layout; integrated circuit reliability; protection; 0.6 micron; 4000 V; 700 V; CMOS output buffer; ESD stresses; LDD process; NMOS devices; NTLSCR devices; PMOS devices; PTLSCR devices; area-efficient output buffer; deep submicron CMOS ASIC; high ESD reliability; high-density applications; lateral SCR device; layout area; polycide process; Application specific integrated circuits; CMOS integrated circuits; CMOS process; CMOS technology; Electrostatic discharge; MOS devices; Protection; Resistors; Robustness; Stress;
Conference_Titel :
ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2707-1
DOI :
10.1109/ASIC.1995.580696
