Cost-effective process integration for a high performance 0.5 μm CMOS logic device

Author

Kim, Young-Wug ; Kim, Yongsik ; Oh, Chang-Bong ; Kim, Bong-Seok ; Yoon, Jong Shik ; Kim, Bonggi

Author_Institution

Logic PA Team, Samsung Electron. Co. Ltd., Seoul, South Korea

fYear

1995

fDate

18-22 Sep 1995

Firstpage

127

Lastpage

130

Abstract

A high performance and cost-effective process for a 0.5 μm CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process

Keywords

CMOS logic circuits; integrated circuit metallisation; integrated circuit reliability; integrated circuit technology; 0.5 micron; 3.3 V; CMOS logic device; COPHOS process; SOG etchback; cost-effective process; electrical properties; high performance logic; insitu Al reflow technique; multilevel interconnects; photoresist etchback; quasi-global inter-metal-dielectric planarization; reliabilities; submicron process integration; CMOS process; Contacts; Costs; Etching; Isolation technology; Logic devices; Planarization; Production; Resists; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580697

Filename

580697