On the re-quantization of data to implement high-order narrow-band filters using reconfigurable logic

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. A method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The reduced bit length representation of the re-quantized input samples removes the requirement for a full multiplier in the filter hardware. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. Using a bit-serial approach, a 100 tap narrow-band filter operating at a sample rate of 1.56 MHz has been developed. A 20 tap bit-parallel filter can be accommodated in one XC4010PG191-4 and operates at a sample rate of 22.6 MHz.