2.5 Gbit/s ATM switch chip set

Author

Plaza, Pierre ; Merayo, Luis ; Diaz, Juan Carlos ; Conesa, Jose Luis

Author_Institution

Telefonica Investigacion y Desarrollo, Madrid, Spain

fYear

1995

fDate

18-22 Sep 1995

Firstpage

173

Lastpage

176

Abstract

The design and implementation of two application specific integrated circuits used to build an ATM switch are here described, the chip set is composed of: 1) the CMC which is an input/output processor of ATM cells implemented on a BiCMOS 0.7 micron technology; and 2) the ICM, a 0.7 micron CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output

Keywords

BiCMOS digital integrated circuits; CMOS digital integrated circuits; application specific integrated circuits; asynchronous transfer mode; digital signal processing chips; electronic switching systems; parallel processing; semiconductor switches; 0.7 micron; 2.5 Gbit/s; 68 MHz; ASIC; ATM switch chip set; BiCMOS technology; CMOS IC; application specific integrated circuits; cell switching; input/output processor; parallelism; segmentation; Asynchronous transfer mode; BiCMOS integrated circuits; CMOS process; Fabrics; Microcell networks; Microprocessors; Routing; Switches; Switching circuits; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International

Conference_Location

Austin, TX

ISSN

1063-0988

Print_ISBN

0-7803-2707-1

Type

conf

DOI

10.1109/ASIC.1995.580708

Filename

580708